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1 ? fn8125.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005-2006. all rights reserved all other trademarks mentioned are the property of their respective owners. x5001 cpu supervisor features ? 200ms power-on reset delay ?low v cc detection and reset assertion ?five standard reset threshold voltages ?adjust low v cc reset threshold voltage using special programming sequence ?reset signal valid to v cc = 1v ? selectable nonvolatile watchdog timer ?0.2, 0.6, 1.4 seconds ?off selection ?select settings through software ? long battery life with low power consumption ?<50a max standby current, watchdog on ?<1a max standby current, watchdog off ? 2.7v to 5.5v operation ? spi mode 0 interface ? built-in inadvertent write protection ?power-up/power-down protection circuitry ?watchdog change latch ? high reliability ? available packages ?8 ld tssop ?8 ld soic ?8 ld pdip ? pb-free plus anneal available (rohs compliant) description this device combines three popular functions, power- on reset, watchdog timer, and supply voltage supervision in one package. this combination lowers system cost, reduces board space requirements, and increases reliability. the watchdog timer provides an independent protec- tion mechanism for microc ontrollers. during a system failure, the device w ill respond with a reset signal after a selectable time out interval. the user selects the interval from three preset values. once selected, the interval does not change, ev en after cycling the power. the user?s system is prot ected from low voltage condi- tions by the device?s low v cc detection circuitry. when v cc falls below the minimum v cc trip point, the system is reset. reset is asserted until v cc returns to proper operating levels and stabilizes. five industry standard v trip thresholds are available, however, intersil?s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the thresh- old for applications requiring higher precision. the device utilizes intersil?s proprietary direct write ? cell for the watchdog timer control bits and the v trip storage element, providing a minimum endurance of 100,000 write cycles and a minimum data retention of 100 years. block diagram watchdog timer data register command decode & control logic si so sck cs /wdi v cc watchdog transition detector reset & watchdog timebase power-on/ generation v trip + - rese t reset low voltage data sheet may 30, 2006
2 fn8125.1 may 30, 2006 ordering information part number part marking v cc range (v) v trip range temp. range (c) package pkg. dwg. # x5001p-2.7 x5001p f 2.7 to 5.5 2.55 to 2.7 0 to 70 8 ld pdip mdp0031 x5001pz-2.7 (note) x5001p zf 0 to 70 8 ld pdip (300 mil) (pb-free) mdp0031 x5001pi-2.7 x5001p g -40 to 85 8 ld pdip mdp0031 x5001piz-2.7 (note) x5001p zg -40 to 85 8 ld pdip (300 mil) (pb-free) mdp0031 x5001s8-2.7 x5001 f 0 to 70 8 ld soic (150 mil) mdp0027 x5001s8z-2.7 (note) x5001 zf 0 to 70 8 ld soic (150 mil) (pb-free) mdp0027 x5001s8i-2.7 x5001 g -40 to 85 8 ld soic (150 mil) mdp0027 x5001s8iz-2.7 (note) x5001 zg -40 to 85 8 ld soic (150 mil) (pb-free) mdp0027 x5001v8-2.7 501 f 0 to 70 8 ld tssop (4.4mm) m8.173 x5001v8z-2.7 (note) 5001 fz 0 to 70 8 ld tssop (4.4mm) (pb-free) m8.173 x5001v8i-2.7 501 g -40 to 85 8 ld tssop (4.4mm) m8.173 x5001v8iz-2.7 (note) 5001 gz -40 to 85 8 ld tssop (4.4mm) (pb-free) m8.173 x5001p-2.7a x5001p an 2.85 to 3.0 0 to 70 8 ld pdip mdp0031 x5001pz-2.7a (note) x5001p zan 0 to 70 8 ld pdip (300 mil) (pb-free) mdp0031 x5001pi-2.7a x5001p ap -40 to 85 8 ld pdip mdp0031 x5001piz-2.7a (note) x5001p zap -40 to 85 8 ld pdip (300 mil) (pb-free) mdp0031 x5001s8-2.7a x5001 an 0 to 70 8 ld soic (150 mil) mdp0027 x5001s8z-2.7a (note) x5001 zan 0 to 70 8 ld soic (150 mil) (pb-free) mdp0027 x5001s8i-2.7a x5001 ap -40 to 85 8 ld soic (150 mil) mdp0027 x5001s8iz-2.7a (note) x5001 zap -40 to 85 8 ld soic (150 mil) (pb-free) mdp0027 x5001v8-2.7a 501 an 0 to 70 8 ld tssop (4.4mm) m8.173 x5001v8z-2.7a (note) 5001 anz 0 to 70 8 ld tssop (4.4mm) (pb-free) m8.173 x5001v8i-2.7a 501 ap -40 to 85 8 ld tssop (4.4mm) m8.173 x5001v8iz-2.7a (note) 5001 apz -40 to 85 8 ld tssop (4.4mm) (pb-free) m8.173 x5001pi x5001p i 4.5 to 5.5 4.25 to 4.5 -40 to 85 8 ld pdip mdp0031 x5001piz (note) x5001p zi -40 to 85 8 ld pdip (300 mil) (pb-free) mdp0031 x5001s8 x5001 0 to 70 8 ld soic (150 mil) mdp0027 x5001s8z (note) x5001 z 0 to 70 8 ld soic (150 mil) (pb-free) mdp0027 x5001s8i x5001 i -40 to 85 8 ld soic (150 mil) mdp0027 x5001s8iz (note) x5001 zi -40 to 85 8 ld soic (150 mil) (pb-free) mdp0027 x5001
3 fn8125.1 may 30, 2006 x5001v8 501 4.5 to 5.5 4.25 to 4.5 0 to 70 8 ld tssop (4.4mm) m8.173 x5001v8z (note) 5001 z 0 to 70 8 ld tssop (4.4mm) (pb-free) m8.173 x5001v8i 501 i -40 to 85 8 ld tssop (4.4mm) m8.173 x5001v8iz (note) 5001 iz -40 to 85 8 ld tssop (4.4mm) (pb-free) m8.173 x5001pi-4.5a x5001p am 4.5 to 5.5 4.5 to 4.75 -40 to 85 8 ld pdip mdp0031 x5001piz-4.5a (note) x5001p zam -40 to 85 8 ld pdip (300 mil) (pb-free) mdp0031 x5001s8-4.5a x5001 al 0 to 70 8 ld soic (150 mil) mdp0027 x5001s8z-4.5a (note) x5001 zal 0 to 70 8 ld soic (150 mil) (pb-free) mdp0027 x5001s8i-4.5a x5001 am -40 to 85 8 ld soic (150 mil) mdp0027 x5001s8iz-4.5a (note) x5001 zam -40 to 85 8 ld soic (150 mil) (pb-free) mdp0027 x5001v8-4.5a 501 al 0 to 70 8 ld tssop (4.4mm) m8.173 x5001v8z-4.5a (note) 5001 alz 0 to 70 8 ld tssop (4.4mm) (pb-free) m8.173 x5001v8i-4.5a 501 am -40 to 85 8 ld tssop (4.4mm) m8.173 x5001v8iz-4.5a (note) 5001 amz -40 to 85 8 ld tssop (4.4mm) (pb-free) m8.173 note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number part marking v cc range (v) v trip range temp. range (c) package pkg. dwg. # x5001
4 fn8125.1 may 30, 2006 pin configuration pin description pin (soic/pdip) pin tssop name function 11cs /wdi chip select input. cs high, deselects the device and the so output pin is at a high impedance state. unless a nonvolatile write cycle is underway, the device will be in the standby power mode. cs low enables the device, placing it in the active power mode. prior to the start of any operation after power-up, a high to low transition on cs is required. watchdog input. a high to low transition on the wdi pin restarts the watch- dog timer. the absence of a high to low transition within the watchdog time out period results in reset /reset going active. 22so serial output. so is a push/pull serial data output pin. a read cycle shifts data out on this pin. the falling edge of the serial clock (sck) clocks the data out. 58si serial input. si is a serial data input pin. input all opcodes, byte addresses, and memory data on this pin. the rising edge of the serial clock (sck) latches the input data. send all opcodes (table 1), addresses and data msb first. 69sck serial clock. the serial clock controls the serial bus timing for data input and output. the rising edge of sck latches in the opcode, address, or watchdog bits present on the si pin. the falling edge of sck changes the data output on the so pin. 36v pe v trip program enable. when v pe is low, the v trip point is fixed at the last valid programmed level. to readjust the v trip level, requires that the v pe pin be pulled to a high voltage (15-18v). 47v ss ground 814v cc supply voltage 7 13 reset reset output . reset is an active low, open drain output which goes active whenever v cc falls below the minimum v cc sense level. it will remain active un- til v cc rises above the minimum v cc sense level for 200ms. reset goes active if the watchdog timer is enabled and cs /wdi remains either high or low long- er than the selectable watchdog time out period. a falling edge of cs /wdi will reset the watchdog timer. reset goes active on power-up at 1v and remains active for 200ms after the power supply stabilizes. 3-5,10-12 nc no internal connections 8 ld soic/pdip x5001 cs /wdi so 1 2 3 4 reset 8 7 6 5 v cc v ss sck si sck si v ss v cc cs /wdi so 1 2 3 4 8 7 6 5 8 ld tssop reset v pe v pe x5001 x5001
5 fn8125.1 may 30, 2006 principles of operation power-on reset application of power to the x5001 activates a power- on reset circuit. this circuit goes active at 1v and pulls the reset /reset pin active. th is signal prevents the system micropro cessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. when v cc exceeds the device v trip value for 200ms (nominal) the circuit releases reset , allowing the processor to begin executing code. low voltage monitoring during operation, the x5001 monitors the v cc level and asserts reset if supply voltage falls below a pre- set minimum v trip . the reset signal prevents the microprocessor from operating in a power fail or brownout condition. the reset signal remains active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip for 200ms. watchdog timer the watchdog timer circuit m onitors the microprocessor activity by monitoring the wdi input. the microproces- sor must toggle the cs /wdi pin periodically to prevent a reset signal. the cs /wdi pin must be toggled from high to low prior to the expiration of the watch- dog time out period. the state of two nonvolatile control bits in the watchdog register determine the watchdog timer period. vcc threshold reset procedure the x5001 is shipped with a standard v cc threshold (v trip ) voltage. this value will not change over normal operating and storage conditions. however, in applica- tions where the standard v trip is not exactly right, or if higher precision is needed in the v trip value, the x5001 threshold may be adjusted. the procedure is described in the following sections, and requires the application of a high voltage control signal. setting the v trip voltage this procedure is used to set the v trip to a higher voltage value. for example, if the current v trip is 4.4v and the new v trip is 4.6v, this procedure will directly make the change. if the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. to set the new v trip voltage, apply the desired v trip threshold voltage to the v cc pin and tie the w pe pin to the programming voltage v p . then a v trip programming command sequence is sent to the device over the spi interface. this v trip programming sequence consists of pulling cs low, then clocking in data 03h, 00h and 01h. this is followed by bringing cs high then low and clocking in data 02h, 00h, and 01h (in order) and bringing cs high. this initiates the v trip programming sequence. v p is brought low to end the operation. resetting the v trip voltage this procedure is used to set the v trip to a ?native? voltage level. for example, if the current v trip is 4.4v and the new v trip must be 4.0v, then the v trip must be reset. when v trip is reset, the new v trip is some- thing less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the v trip voltage, apply greater than 3v to the v cc pin and tie the w pe pin to the programming voltage v p . then a v trip command sequence is sent to the device over the spi interface. this v trip pro- gramming sequence c onsists of pulling cs low, then clocking in data 03h, 00h and 01h. this is followed by bringing cs high then low and clocking in data 02h, 00h, and 03h (in order) and bringing cs high. this initiates the v trip programming sequence. v p is brought low to end the operation. x5001
6 fn8125.1 may 30, 2006 figure 1. sample v trip reset circuit figure 2. set v trip level sequence (v cc = desired v trip value) figure 3. reset v trip level sequence (v cc > 3v) 1 2 3 4 8 7 6 5 x5001 v trip adj. v p reset 4.7k si so cs sck c adjust run 012345678910 sck si cs 20 21 22 23 16 bits 0001h 03h 012345678910 20 21 22 23 16 bits 0001h 02h v pe v pe = 15-18v 012345678910 sck si cs 20 21 22 23 16 bits 0001h 03h 012345678910 20 21 22 23 16 bits 0003h 02h v pe v pe = 15-18v 16 bits x5001
7 fn8125.1 may 30, 2006 figure 4. v trip programming sequence spi interface the device is designed to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller families. the device monitors the cs /wdi line and asserts reset output if there is no activity within user select- able timeout period. the device also monitors the v cc supply and asserts the reset if v cc falls below a preset minimum (v trip ). the device contains an 8-bit watchdog timer register to control the watchdog time out period. the current settings are accessed via the si and so pins. all instructions (table 1) and data are transferred msb first. data input on the si line is latched on the first ris- ing edge of sck after cs goes low. data is output on the so line by the falling edge of sck. sck is static, allowing the user to stop the clock and then start it again to resume operations where left off. v trip programming apply 5v to v cc decrement v cc reset pin goes active? measured v trip - desired v trip done execute sequence reset v trip set v cc = v cc applied = desired v trip execute sequence set v trip new v cc applied = old v cc applied + error (v cc = v cc - 50mv) execute sequence reset v trip new v cc applied = old v cc applied - error error < 0 error = 0 yes no error > 0 x5001
8 fn8125.1 may 30, 2006 watchdog timer register watchdog timer control bits the watchdog timer control bits, wd 0 and wd 1 , select the watchdog time out period. these nonvola- tile bits are programmed with the set watchdog timer (swdt) instruction. write watchdog register operation changing the watchdog timer register is a two step process. first, the change must be enabled by setting the watchdog change latch (see below). this instruc- tion is followed by the set watchdog timer (swdt) instruction, which includes th e data to be written (fig- ure 5). data bits 3 and 4 contain the watchdog settings and data bits 0, 1, 2, 5, 6 and 7 must be ?0?. watchdog change latch the watchdog change latch must be set before a write watchdog timer operat ion is initiated. the enable watchdog change (e wdc) instruction will set the latch and the disable watchdog change (dwdc) instruction will reset the latch (figure 6). this latch is automatically reset upon a power-up condition and after the completion of a valid nonvolatile write cycle. read watchdog timer register operation if there is not a nonvolatile write in progress, the read watchdog timer instruction re turns the setting of the watchdog timer control bits. the other bits are reserved and will return?0 ? when read. see figure 3. if a nonvolatile write is in progress, the read watchdog timer register instruction returns a high on so. when the nonvolatile write cycle is completed, a separate read watchdog timer instruction should be used to determine the current status of the watchdog control bits. reset operation the reset (x5001) output is designed to go low whenever v cc has dropped below the minimum trip point and/or the watchdog timer has reached its pro- grammable time out limit. the reset output is an open drain output and requires a pull-up resistor. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? a high to low transition on cs is required to enter an active state and re ceive an instruction. ? so pin is high impedance. ? the watchdog change latch is reset. ? the reset signal is active for t purst . data protection the following circuitry has been included to prevent inadverten t writes: ? a ewdc instruction must be issued to enable a change to the watchdog timeout setting. ?cs must come high at th e proper clock count in order to implement the requested changes to the watchdog timeout setting. table 1. instruction set definition note: instructions are shown with msb in leftmost position. instructions are transferred msb first. 76543210 000wd 1 wd 0 000 watchdog control bits watchdog time out (typical) wd1 wd0 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled instruction format instruction name and operation 0000 0110 ewdc: enable watchdog change operation 0000 0100 dwdc: disable watchdog change operation 0000 0001 swdt: set watchdog timer control bits: instruction followed by contents of register: 000(wd 1 ) (wd 0 )000 see watchdog timer settings and figure 7. 0000 0101 rwdt: read watchdog timer control bits x5001
9 fn8125.1 may 30, 2006 figure 5. read watchdog timer setting figure 6. enable watchdog change/disable watchdog change sequence figure 7. write watchdog timer sequence 01234567 cs sck si so rwdt instruction ... ... ... w d 0 w d 1 01234567 cs si sck high impedance so instruction (1 byte) 0123456789 cs sck si so high impedance instruction 10 11 12 13 14 15 data byte 65 4 3 w d 1 w d 0 x5001
10 fn8125.1 may 30, 2006 figure 8. read nonvolatile status (option 1) (used to determine end of wa tchdog timer store operation) figure 9. read nonvolatile status (option 2) (used to determine end of wa tchdog timer store operation) 01234567 cs sck si so rwdt instruction so high during 1st bit while in the nonvolatile write cycle nonvolatile write in progress 01234567 cs sck si so rwdt instruction so high during nonvolatile write cycle nonvolatile write in progress x5001
11 fn8125.1 may 30, 2006 absolute maximum ratings temperature under bias ................... -65c to +135c storage temperature ............ ............ -65c to +150c voltage on any pin with respect to v ss ...................................... -1.0v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10s) .................... 300c comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this datasheet) is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect device reliability. d.c. operating characteristics (over the recommended operating cond itions unless otherwise specified) symbol parameter limits unit test conditions min. typ max. i cc1 v cc write current (active) 5masck = v cc x 0.1/v cc x 0.9 @ 5mhz, so = open i cc2 v cc read current (active) 0.4 ma sck = v cc x 0.1/v cc x 0.9 @ 5mhz, so = open i sb1 v cc standby current wdt=off 1acs = v cc , v in = v ss or v cc , v cc = 5.5v i sb2 v cc standby current wdt=on 50 a cs = v cc , v in = v ss or v cc , v cc = 5.5v i sb3 v cc standby current wdt=on 20 a cs = v cc , v in = v ss or v cc , v cc = 3.6v i li input leakage current 0.1 10 a v in = v ss to v cc i lo output leakage current 0.1 10 a v out = v ss to v cc v il (1) input low voltage -0.5 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage 0.4 v v cc > 3.3v, i ol = 2.1ma v ol2 output low voltage 0.4 v 2v < v cc < 3.3v, i ol = 1ma v ol3 output low voltage 0.4 v v cc 2v, i ol = 0.5ma v oh1 output high voltage v cc -0.8 v v cc > 3.3v, i oh = -1.0ma v oh2 output high voltage v cc -0.4 v 2v < v cc 3.3v, i oh = -0.4ma v oh3 output high voltage v cc -0.2 v v cc 2v, i oh = -0.25ma v olrs reset output low voltage 0.4 v i ol = 1ma recommended operating conditions note: pt= package, temperature temperature min. max. commercial 0c +70c voltage option supply voltage limits -1.8 1.8v to 3.6v -2.7 or -2.7a 2.7v to 5.5v -4.5 or -4.5a 4.5v to 5.5v x5001
12 fn8125.1 may 30, 2006 power-up timing capacitance (t a = +25c, f = 1mhz, v cc = 5v) notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. equivalent a.c. load circuit a.c. test conditions a.c. characteristics (over recommended operating condit ions, unless otherwise specified) data input timing symbol parameter min. max. unit t pur (2) power-up to read operation 1 ms t puw (2) power-up to write operation 5 ms symbol test max. unit conditions c out (2) output capacitance (so, reset )8pfv out = 0v c in (2) input capacitance (sck, si, cs )6pfv in = 0v 3v output 100pf 5v 3.3k ? reset 30pf 1.64k ? 1.64k ? input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x0.5 symbol parameter 1.8v-3.6v 2.7v-5.5v unit min. max. min. max. f sck clock frequency 0 1 0 2 mhz t cyc cycle time 1000 500 ns t lead cs lead time 400 200 ns t lag cs lag time 400 200 ns t wh clock high time 400 200 ns t wl clock low time 400 200 ns t su data setup time 100 50 ns t h data hold time 100 50 ns t ri (3) input rise time 2 2 s t fi (3) input fall time 2 2 s t cs cs deselect time 250 150 ns t wc (4) write cycle time 10 10 ms x5001
13 fn8125.1 may 30, 2006 data output timing notes: (3) this parameter is periodically sampled and not 100% tested. (4) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. figure 10. data output timing figure 11. data input timing symbol parameter 1.8v-3.6v 2.7v-5.5v unit min. max. min. max. f sck clock frequency 0 1 0 2 mhz t dis output disable time 400 200 ns t v output valid from clock low 400 200 ns t ho output hold time 0 0 ns t ro (3) output rise time 300 150 ns t fo (3) output fall time 300 150 ns sck cs so si msb out msb?1 out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance x5001
14 fn8125.1 may 30, 2006 symbol table figure 12. power-up and power-down timing reset output timing note: (5) this parameter is periodically sampled and not 100% tested. pt = package, temperature waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance symbol parameter min. typ. max. unit v trip reset trip point voltage, x5001pt-4.5a reset trip point voltage, x5001pt-4.5 reset trip point voltage, x5001pt-2.7a reset trip point voltage, x5001pt-2.7 reset trip point voltage, x5001pt-1.8 4.50 4.25 2.85 2.55 1.70 4.63 4.38 2.92 2.63 1.75 4.75 4.50 3.00 2.70 1.80 v t purst power-up reset timeout 100 200 280 ms t rpd (5) v cc detect to reset/output 500 ns t f (5) v cc fall time 0.1 ns t r (5) v cc rise time 0.1 ns v rvalid reset valid v cc 1v v cc t purst t purst t r t f t rpd reset (x5001) 0 volts v trip v trip x5001
15 fn8125.1 may 30, 2006 figure 13. cs vs. reset timing reset output timing v trip programming timing diagram symbol parameter min. typ. max. unit t wdo watchdog timeout period, wd 1 = 1, wd 0 = 0 wd 1 = 0, wd 0 = 1 wd 1 = 0, wd 0 = 0 100 450 1 200 600 1.4 300 800 2 ms ms sec t cst cs pulse width to reset the watchdog 400 ns t rst reset timeout 100 200 300 ms cs t cst reset t wdo t rst t wdo t rst sck si cs 0001h or 02h v cc (v trip ) v pe t tsu t thd t vph t vps v p v trip t rp t vpo t pcs 0003h 0001h 03h x5001
16 fn8125.1 may 30, 2006 v trip programming parameters parameter description min. max. unit t vps v trip program enable voltage setup time 1 s t vph v trip program enable voltage hold time 1 s t pcs v trip programming cs inactive time 1 s t tsu v trip setup time 1 s t thd v trip hold (stable) time 10 ms t wc v trip write cycle time 10 ms t vpo v trip program enable voltage off time (between successive adjustments) 0 s t rp v trip program recovery period (between successive adjustments) 10 ms v p programming voltage 15 18 v v tran v trip programmed voltage range 1.7 5.0 v v ta1 initial v trip program voltage accuracy (v cc applied-v trip ) (programmed at 25c) -0.1 +0.4 v v ta2 subsequent v trip program voltage accuracy [(v cc applied-v ta1 )-v trip . programmed at 25c.] -25 +25 mv v tr v trip program voltage repeatability (successive program operations. programmed at 25c.) -25 +25 mv v tv v trip program variation after programming (0 -75c). (programmed at 25c) -25 +25 mv v trip programming parameters are periodica lly sampled and are not 100% tested. x5001
17 fn8125.1 may 30, 2006 watchdog timer on (v cc = 5v) watchdog timer on (v cc = 3v) watchdog timer off (v cc = 3v, 5v) -40c 25c 90c temp (c) isb (a) v cc supply current vs. temperature (i sb )t wdo vs. voltage/temperature (wd1, 0 = 1, 1) v trip vs. temperature (programmed at 25c) t wdo vs. voltage/temperature (wd1, 0 = 1, 0) t purst vs. temperature t wdo vs. voltage/temperature (wd1, 0 0 = 0, 1) 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.7 3.1 4.5 90c 25c -40c reset (seconds) voltage 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 025 85 voltage temperature v trip = 5v v trip = 3.5v v trip = 2.5v 0.85 0.80 0.75 0.70 0.65 0.60 1.7 4.5 reset (seconds) voltage 3.1 90c 25c -40c 275 270 265 260 255 250 245 240 235 -40 25 90 degrees c 280 time (ms) 90c 25c -40c 0.28 0.27 0.26 0.25 0.24 0.23 0.22 0.21 0.20 0.29 reset (seconds) voltage 1.7 3.1 4.5 14 11 17 15 20 18 0.35 0.55 1.0 0.30 x5001
18 fn8125.1 may 30, 2006 x5001 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) tolerance notes a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. l 2/01 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
19 fn8125.1 may 30, 2006 x5001 plastic dual-in-line packages (pdip) notes: 1. plastic or metal protrusions of 0.010? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions e and ea are measured with the l eads constrained perpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. mdp0031 plastic dual-in-line package symbol pdip8 pdip14 pdip16 pdip18 pdip20 tolerance notes a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. b 2/99 d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8125.1 may 30, 2006 x5001 thin shrink small outlin e plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dam bar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material conditi on. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m8.173 8 lead thin shrink narrow body small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n8 87 0 o 8 o 0 o 8 o - rev. 1 12/00

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